1. Field of the Invention
The present invention relates to the field of hybrid circuits, and more particularly to hybrid circuits for interconnecting unpackaged integrated circuits.
2. Prior Art
Hybrid circuits of various forms are well-known in the prior art. Such circuits have been generally used for the high density packaging of active and passive devices, more recently integrated circuits, discreet components and the like in a high density configuration. The densities that normally have been obtainable in the more conventional hybrid circuits are much higher than obtainable with packaged devices using conventional integrated circuit technology.
More recently, surface mount technology (SMT) methods have been used to at least approach the density of packaging theretofore obtainable in the prior hybrid circuits. In accordance with SMT, integrated circuits, discreet components, arrays of components, etc., are packaged not in the usual dual-in-line packages with conventional leads, lead spacing, etc., but rather with a minimal sized protective coating with relatively tightly spaced connection pads on one surface thereof. These SMT devices are typically solder bonded to an appropriately laid out and tightly packed printed circuit board to result in the required circuit board area for a given circuit which is only a fraction of that obtainable with conventional dual-in-line (DIP) packaging and printed circuit board layout techniques. Further, automatic SMT device mounting equipment and bonding equipment keeps the cost of SMT circuits down, particularly in high quantities, making this technology applicable even to consumer products. Also, in very recent years, there has been a considerable effort to develop larger and larger scale integrated circuits, with an ultimate goal of achieving wafer scale integration. While progress has been made in this direction, particularly with respect to microprocessor and microcomputer chip sets, the progress in other areas has been disappointingly slow to many people for various reasons. Smaller and smaller device sizes and line widths in integrated circuits have allowed substantial increases in integrated circuit complexity without requiring an equal increase in chip area. Further, except for microprocessor chip sets and memory devices wherein more is always better, it has been difficult to identify standardized functions for LSI and larger integrated circuits which will have a sufficient market volume to justify the same.
In addition to the foregoing, very large scale and larger integrated circuits generally have a bad yield problem which may only be overcome, at least in part, by providing on chip redundancy. In particular, a common approach to the yield problem is to provide redundancy for each functional part of the circuit, thereby increasing the required chip area by approximately 100 percent. While such redundancy can dramatically increase the yields by now requiring only one out of two of each functional block circuits to operate, rather than one out of one which would be required without redundancy, the effect of the redundancy is not only to increase chip size, but also to cause relatively long interconnects which substantially slow down the circuit because of the resulting relatively high parasitic capacitance.
As a result, considerable interest has developed in forming multi-chip modulus wherein a plurality of integrated circuits in chip form are mounted on a substrate and interconnected to provide the functions of VSLI and higher integration without the normally associated problems thereof. Such interconnecting devices, sometimes referred to as high density multi-layer interconnects (HDMI), allow the testing of individual integrated circuits before mounting, thereby eliminating the need for redundancy for suitable yields. This can allow closer connection of the functional blocks on the HDMI than could be achieved in a corresponding single chip device. In many cases, it can also result in a faster circuit by reducing parasitic capacitance, can eliminate the need for on-chip line drivers sometimes required because of the long interconnect lines on large single chip integrated circuits, can reduce costs by allowing testing of the integrated circuit functional blocks and the elimination of only the bad ones before using the same in the HDMI, and of course allows one to obtain the advantages of wafer scale integration without the attendant problems thereof even in applications wherein the market volume for the product is too small to consider larger scale or wafer scale integration.
At the present time, HDMI technology is somewhat of a mix, in some ways resembling integrated circuit fabrication techniques and in other ways somewhat resembling printed circuit board techniques. By way of example, conductor line widths are beginning to approach those used in at least older integrated circuit designs, and bonding techniques used to interconnect the chips to the HDMI are those typically used in conventional integrated circuit packaging. On the other hand, the materials used for the insulative layers, typically polymers, and the number of cross-overs required are more similar to that found in printed circuit board fabrication, as opposed to the silicon-oxide layer and the deposited metal interconnect layer of typical integrated circuits.
In the detailed description to follow, where relevant, specific prior art techniques will be identified as they more specifically relate to the new methods and structures disclosed herein.